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μ PD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Bus Cycle State Diagram
LOAD NEW
WRITE ADDRESS;
W_Count = 0
LOAD NEW
READ ADDRESS;
R_Count = 0;
R_Init = 1
Always
W# = LOW & W_Count = 4
R# = LOW & R_Count = 4
Always
W# = LOW
WRITE DOUBLE;
W_Count = W_Count+2
R# = HIGH
& R_Count = 4
READ DOUBLE;
R_Count = R_Count+2
R_Init = 0
W_Count = 2
Always
R_Count = 2
Always
R# = LOW
W# = HIGH
INCREMENT WRITE
ADDRESS BY TWO
W# = HIGH
& W_Count = 4
INCREMENT READ
ADDRESS BY TWO
R_Init = 0
R# = HIGH
WRITE PORT NOP
Supply voltage
Power UP
Supply voltage
READ PORT NOP
R_Init = 0
provided
provided
Remarks 1. The address is concatenated with two additional internal LSBs to facilitate burst operation.
The address order is always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3.
Bus cycle is terminated at the end of this sequence (burst count = 4).
2. Read and write state machines can be active simultaneously.
Read and write cannot be simultaneously initiated. Read takes precedence.
3. State machine control timing is controlled by K.
Data Sheet M19962EJ2V0DS
13
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